1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and, more particularly, to an input/output circuit for inputting/outputting data in synchronization with a clock as well as to a synchronous semiconductor memory device including the input/output circuit.
2. Description of the Background Art
Conventionally, in a data input/output circuit used in a semiconductor device, for example in a semiconductor memory device, a plurality of data to be output are shifted or offset in phase with respect to an internal clock, so as to enable data transfer from the semiconductor memory device at a rate higher than the clock frequency.
As the speed of operation of semiconductor devices has been increased recently, however, there arises a problem of data collision or erroneous data pickup when a plurality of data are interleaved and picked up by an externally connected circuit.
In a very large synchronous semiconductor memory device having as large a memory capacity as 1 G bit, there is considerably large skew in internal signals, especially in a clock controlling the overall operation of the chip, which skew limits the operational frequency of the chip. Especially when an externally input reference clock is received by a clock buffer and addresses, data and commands are received based on the clock, it is necessary to distribute the received clock to respective address, data and command input terminals. Delay involved in the clock distribution limits performance of the chip. Further, at the time of output, if the output buffer is controlled based on the clock, the output is delayed by the amount of clock skew, which may reduce margin of the output data received externally.
As a second problem, the following is experienced in an operation test during manufacturing or before shipment of the product, as the speed of operation of the semiconductor memory device has been increased.
More specifically, as the storage capacity of the semiconductor memory device increases, the time necessary for testing the device increases and, eventually, the cost for the test and manufacturing cost of the product have been increased.
As a measure to address the increased test time associated with increased storage capacity of the semiconductor memory device, efficiency of testing is improved by testing a plurality of semiconductor memory devices in parallel. The increased storage capacity of the semiconductor memory device mentioned above involves increased number of bits of the address signals to be applied to the semiconductor memory device and multiple bits data input/output interface, and therefore the number of pins for control signals and input/output pins per one semiconductor memory device are increased. Accordingly, the number of semiconductor memory devices which can be tested in parallel at one time is limited.
The number of chips of the semiconductor memory devices which can be measured at one time by a tester is determined by the relation between the number of pins of the tester and the number of pins required by the chip, which relation is generally represented by the following equation. EQU (Number of pins of the tester)/(number of pins required by the chip)&gt;(number of chips measurable at one time)
Further, if the speed of operation of a tester for testing the semiconductor memory device is to be improved along with the improvement of the speed of operation of the semiconductor device, very expensive testing apparatus is necessary, which results in increased cost of testing.
A third problem is that in a synchronous semiconductor memory device attaining reduced cost and improved function by employing complicated system such as BIST (Built In Self Test) and clock generation by DLL (Delay Locked Loop), it is difficult to monitor state of operation of this circuit externally.